Data signal processing apparatus



56N' 24, 1963 B. M. GORDON ETAL 3,105,231

DATA SIGNAL PROCESSING APPARATUS 3 Sheets-Sheet 1 Filed Nov. 5. 1958 mvmm* mo S532 mDOOmQ KSPJDE MUN IN V EN TORS BERNARD M. GORDON ROBERT P. TALAMBIRAS AT ORNEY Sept. 24, 1963 B. M. GORDON ETAL 3,105,231

DATA SIGNAL PROCESSING APPARATUS Filed Nov. 3, 1958 5 Sheets-Sheet 2 Sept.`24, 1963 a.'v M. GORDON ETAL i 3,105,231 DATA SIGNAL PROCESSING APPARATUS v Filed Nov. s. 195s s sheets-sheet a l lIJ JNVENTgRsO ERNARD M. G R N YROBERT R TALAMBIRAS ATT RNEY 20m msmm l l 1 No.

United States Patent 3,105,231 BATA SIGNAL PRCESSING APPARATUS Bernard M. Gordon, Newton, and Robert P. Talarnbiras,

Boston, Mass., assig'nors to Epsco Incorporated, Boston, Mass., a corporation of Massachusetts Filed Nov. 3, 1958, Ser. No. '771,664 7 Claims. (Cl. 340-347) The present invention relates in general to data processing and more particularly concerns .novel apparatus Ifor converting a number of input analog signals into digital form with great accuracy in a relatively short time. 'This is accomplished without multiplexing and utilizes circuitry in which the num-ber of critical parameters is minimized.

When makin-g tests of complex systems, it is frequently necessary to continuously monitor data signals from a number of sources. Typically these signals are provided by strain guages and thermocouples located at various points within and near the system under test. In order to evaluate the system, data processing machines are often employed to process the monitored data. A high degree of accuracy is more readily obtained i-f digital data processing systems operate upon this data. Since the data signals are generally in analog form, the monitored data signals must first be converted into digital form. If the Ifull accuracy of the digital data processing system is to be realized, the conversion into digital form must be effected with great accuracy. Since accurate analog to digital converters are costly, it is common practice to use multiplexing techniques to connect the different signals in sequence to a single converter.

However, the multiplexing system itself is often a source of error. Multiplexing systems in which this error is minimized to a tolerable level are generally costly and introduce additional components subject to failure.

Accordingly, the present invention contemplates and has as 4a primary object the accurate convension of la number of input analog signals into digital form.

It is another object of the invention to achieve the preceding object without multiplexing and with apparatus which lfunctions with great reliability.

It is still another object of the invention to provide a relatively large number of conversions per unit time interval.

Another object of the invention is to provide means for storing each conversion in a location corresponding to the analog signal which it represents.

A further object yof the invention is to ciurther store a vframe number with conversions corresponding to the level of the input signals at 1a particular time to identify the order in which the stored ldigital numbers must be reassembled to correctly represent the input analog signals.

Still another object of the invention is to hold the levels of the input analog signals to respective values which occur at the same time and convert the levels thus held into digital numbers.

According to the invention, means are provided rfor developing a decoded analog signal which changes amplitude by stepwise increments corresponding to changes in Value of `a digital number. The decoded analog signal is compared with each of the input analog signals to provide a comp-are signal identifying the one or more input analog signals then diiering from the decoded analog signal Iby sa predetermined amount. The value of the digital number at this time is then transferred into those portions of `a storage system asociated with the one or more analog signals thus identified. The decoded analog signal is stepped through a range sufcient to cause each input analog signal to be converted into a corresponding digital number. Then, the stored numbers may be transferred to an external circuit.

ice

Other features, objects and advantages lof the invention will become apparent from the following specification when read in connection with the accompanying drawing in which:

FIG. 1 is la block diagram illustrating the logical arrangement of -a preferred embodiment :of the invention;

FIG. 2 shows a block diagram of the programmer represented as a single block in FIG. l;

FIG. 3 is a schematic representation of a shift register for temporarily storing the digital number from a sampled channel; and

FIG. 4 is a schematic circuit diagram of la preferred embodiment of a multiar comparator.

With reference now to the drawing and more particularly FG. l thereof, there is illustrated a block diagram showin-g the logical arrangement of a preferred embodiment of the novel system. The input analog signals applied on respective input terminals 11 are encoded into a sequence of decimal digits each represented by four binary bits provided in parallel on the :tour output terminals 12. Before discussing in detail the mode of operation, the physical arrangement and logic of the system will be described. For each input analog signal, there is a separate channel. Each channel includes a chopper stabilized amplifier 13, la hold circuit 1G, a multiar comparator 14 and a channel comparis-on dip-flop 15. A counter 16 is advanced by count pulses supplied on line 17' Ifrom programmer 18.

A decoder 21 responds to the count representing a digital number in counter 16 by providing a decoded analog signal representative of the count on line 22. An off-set flip-flop 20 is set and reset at appropriate times, by signals on lines 23 and 24, respectively, from programmer 18. When set this flip-flop provides a potential for offsetting the decoded analog signal for reasons explained below.

The deco-ded .analog signal is applied jointly to the inputs of the comparators 14. Each comparator is energized respectively from. a hold circuit 10 which samples the amplied input analog signal from an associated amplier 13 and holds the value thereof at the time a Hold signal is `delivered on line 35. When the difference between the decoded analog lsignal and the respective input analog signal is less than a predetermined magnitude, a comparator 14 delivers a signal to the associated channel comparison Hip-flop 15 which sets the dip-flop to cause a compare signal conditioning potential to be delivered on the associated output line 25. When any one or more of lines 25 is conditioned, an associated AND gate 26 is enabled and programmer 18 responds by delivering suitable con-trol pulses nor transferring Ithe count then in counter 16 through encoding gates 19 into storage register 28.

During each cycle of operation, the counter 16 is stepped by increments corresponding to single changes in the least signicant digit of a digital number represented by its state. These changes occur between the greatest and least values of the digital number over a range sufcient to digitalize all input signal amplitudes. In the exemplary 4embodiment of this invention, lthe digital number represented has three decimal digits and the least significant digit is binary, corresponding to a decimal value of 0 or `0.5. In addition, an indication of the sign of the digital number may be represented as a binary digit in the counter so that the digital number represented by the counter assumes the range of values in steps of 0.5 between +9995 to 999.5. At the completion of a cycle, counter 16 delivers a carry pulse on line 31 which sets the frame read dip-flop 32. When flip-Hop 32 is set, the number in digital form stored in frame counter 33 may be transferred through frame count encoding gates 34 into an appropriate position in storage register Ymay be used to designate this value.

28 to identify the set of digital numbers then stored. This transfer is initiated by the programmer in response to the carry pulse. K

In a preferred form of operation, each hold circuit includes a capacitor or other suitable storage device for Y holding the level of the associated input analog signal to that which occurred at the time hold line 35 is conditioned by programmer 18. During each cycle of the counter 16, each of the levels thus held is converted into a digital number which is stored in an associated portion of storage register'ZS when la gate 26 is conditioned by an associated channel comparison hip-flop 15.r If two or more channel levels are the same, the digital numbers characteristic thereof will be transferred into appropriate portions of storage register 2S at the same time.

The foregoing brief description should facilitate any understanding of the detailed description of the mode of operation which follows.V

It is convenient to yinitially assume that count pulses i delivered from programmer 18 are stepping the count in counter 16. The decoded Yanalog signal on line 22 is then changing lby stepwise increments having a magnitude equal to the analog equivalent ofthe least significant digit stored in counter 16. For this specific example, this increment corresponds to decimal 0.5. When the difference between the decoded analog'signal on line 22 and an input analog signal delivered by an amplifier 13 is less than the magnitude of this increment, a comparator 14 delivers an output signal which sets flip-flop 15. When a dip-flop is set, an output line 25 is conditioned and associated gates 26 Vare enabled while programmer 18 is activated to provide control signals for transferring the digital number electrically represented by the state of counter 16 through encoding gates 19 into portions of storage register 2S associated with the enabled ones of V 'Before continuing with the explanation of how they temporarily unchanged digital number represented by the state of counter 16 is transferred linto storage, it is Y appropriate to consider generally the nature of counter 16. In this exemplary embodiment, this counter consists of five cascaded stages. The first .st-age 36 is a binary counter which changes its state in response to each count pulse delivered on line 17 to deliver a signal on vline 37 indicative of the least significant digit. The second stage 38 is a conventional four-stage decode sealer which changes its state once for every two count pulses delivered on line 17. Fourv output lines deliver potentials representative of the value of the units digit. Various codes It has been found satisfactory to use the 8-4-2l excess three system of representing the decimal digit. In thissystem of representa- 4 y the count of counter 16 down by 0.5. Thus, after the delivery of 1,999pulses on line 17, the digital number represented is +OO0.0.and the next pulse resets all three decimal stages to 9 and the least significant digit to .5 while delivering a carry pulse to stage 43 to change its state, thereby indicating a minus sign. After 1,999 additional pulses are delivered on line 17, the digital number represented by the counter is 100.0. The 4,000th pulse delivered on line 17 clears the counter back to +9995, completing a cycle. The decoded analog signal from decoder 2,1V developed is stepped linearly from i cuit 1t) as described previously.

tion, the four output lines are WeightedV as l, 2, 4, and 8,

count pulse delivered on line 17 is effective in stepping,

f Because of the nature of the number progression, those numbers which are preceded by a minus sign are the ,complement of the digital number Ythen represented by the decoded analog signal. In some digital computers`,'nega tive numbers are complemented while positive numbers are not so that all the numbers represented in this form may be used directly. However, if the digital numbers are to be utilized in terms of actual magnitude kand sign,

any well-known technique kof complementing may be used Y to change the negative number into the desired form.

Having discussed the nature of the digital numbers, it is appropriate to resume the consideration of how the numbers are transferred into storage. Each digital number is represented by four words composed of'no more than four binary bits. The first Word includes the least signicant digit and sign in the rst and fourth bits, respectively, the second and third bits being unused. The second, third, and fourth Words represent the units, tens, andhundredths digits, respectively, of the digital number. In each Word, the first, second, third and fourth bits correspond to counter lines Weighted l,V 2, 4, and 8, respectively. The `storage register 28 consists of four shift registers arranged whereby a column including a core from each register stores the four bits of a word. A portion of the storage register comprising five consecutive columns is used to accept a block of four words. The first column of each group of ve accepts all words being inserted into storageV regardless of Whether the word is addressed to that group or not. group are shifted in sequence from the first column to the remaining four.

The four words are transferred into storage in response to timing pulses T1, T2, T3, T4 and T5 delivered in that order on lines 44, 45, 46, 47 andk 48 respectively, and shift pulses delivered on line 50 through enabled ones of gates 26 and 27 ian'd ybuffers 52 to shift pulse amplifiers 53 and then to the shift windingsof those cores in the associated group.

Ther block 19` of encoding gates is represented as divided into four sect-ions. Each of the sections correspond to,r one of the Words to be inserted into storage andthe four encoding output lines from each form, a part of cable 49. All portions of the encoding gates l are .energized by the core input sample pulse delivered on line 51. However, these portions `are respectively energized by'timing pulses T1, T2, T3 and T4 which occur in that sequence. The output lines from Ian encoding :gate portion will be activated only if a core input sample Ipulse occurs concurrently with a Ytiming pulse; therefore, the lines in cable 49 are activated in sequence with signals characteristic of the four bits in Words 1-4 Before each timing pulse, `a shift pulse is provided on line 50. yThese shift pulses are passed by only the enabled ones of gates 26 and 27. During the course of a transfer cycle, one vor more of the gates 26 Vwill be enabled'and the associated portion of the storage register 2S energized with shift pulses so that each word is shifted into the following column in the selected groupuntil words 1, 2, 3, and 4 are stored in columns 5, 4, 3, and 2, respectively. Then, timing pulse T5 is vgener-ated, re-v Words addressed to a setting all the channel comparison flip-flops 15 and the offset liip-flop 23 and count pulses are again delivered on line 17 until the next compare signal is provided. The sequence of events described above is then repeated.

After counter 16 has cycled throughall values, each of -the previously held levels of the input signals has been converted into a digital number which is stored in the appropriate portion of storage register 28 and a carry pulse is delivered on line 31 to set frame read flip-flop 32 and thereby disable gate 29 while enabling gate 3l)l so that the sample pulse on line 51 is applied to the frame ycount encoding gates 34. The carry pulse also resets each multiar comparator.

Frame counter 33 consists of four cascaded decade scalers land its state is representative of a four digit decimal number. In a manner similar to that described above lwith respect to counter 16 and gates 27, output potentials -from frame counter 33 are transferred to the frame portion of storage register 28 through frame count encoding 'gates 34 and cable 49. The count in frame counter 33 is then advanced by one in response to an advance pulse delivered on line 54 from pro-grammer 13. Count pulses are again temporarily not delivered on line 17 and the hold potential on line 35 is removed so that the storage elements in each hold circuit may assume levels consistent with the values -o-f the respective input analog signals at this time prior to initiation of another digitalizing cycle.

Having described the overall system, it is appropriate to cons-ider certain portions thereof in greater detail. Referring to FIG. 2, there is shown in block diagram form the logical larrangement of programmer 18. The output terminals on the right bear the same reference numeral as corresponding lines emanating `from programmer 18 in FIG. l. A switch 61 is used to select signals which determine how often counter 16 is cycled. When connected to sampling oscillator 62 as shown, the number of pulses per unit time from oscillator 62 determines the rate of conversion. Typically, sampling oscillator 62 provides l0 pulses per second so that each of the N channels is sampled ten times per second.

When connected to terminal 63, external sampling pulses applied to terminal 64 determine the sampling rate.

When switch 61 is connected to scaler 65 energized by the output of sampling oscillator 62, the sampling rate of the latter is effectively reduced. Typically, this reduction is by a factor of ten sothat each input analog signal is sampled once per second.

A start signal applied to the set input of start flip-flop 66 conditions gate 67 to .pass the sampling pulses delivered by switch 61, thereby triggering blocking oscillator 68. Blocking oscillator 63 responds by providing an output pulse which sets hol-d flip-flop 71. This output pulse is also passed through buffer 72 as the set signal delivered by terminal 23 for setting offset flip-flop 20.

In addition, this pulse is utilized as an advance pulse on terminal S4 for advancing the count of frame counter l The output pulse from blocking oscillator 68 is also passed through buffer 73 to set sweep control ilip-flop 74 after ybeing delayed by delay unit 75 for a time interval sufficient to allow offset flip-flop 20 to lstabilize after being reset.

When sweep control flip-flop 7d is set, it conditions gate 76 to pass ycount pulses from counter oscillator 77 to count terminal 17. A typical pulse rate from counter oscillator 77 is 125 kilocycles.

When one of the compare terminals 25' is conditioned, the change in potential is differenti-ated hy capacitor S1 to provide a pulse for triggering blocking oscillator 32. The output pulse from blocking oscillator 82 is transmitted through buffer 72 to set terminal 23 for setting offset flip-flop 20. Also, this pulse is coupled through buffer 84a to the reset input of sweep control flip-flop 74.

This resets flip-flop 74, thereby disabling gate 76 so that counter oscillator 77 no longer delivers count pulses to terminal 17.

The output pulse from blocking oscillator 82 is effective in initiating a read sequence yby which a digital number is transferred into storage register 28.

This output pulse sets read flip-flop 83 to condition gate 84. When gate 84 is conditioned, it delivers pulses from sequencing oscillator 85 to a delay flop 86. rIhe delay flop 86 furnishes enough delay so that transients due to the sequence of events which occur upon the occurrence of a compare signal have died out. The delayed sequencing pulses from delay lop 86 are delivered to terminal t5 and utilized as shift pulses. The delayed pulses 'from a second output of delay flop 86 are applied to a delay unit 87 which provides sample pulses on terminal 51.

The delayed sequencing pulses from delay Hop 86 are Lalso applied to sequencing counter 91 which responds by providing live Itiming pulses in sequence on terminals Lit-4,8. Sequencing counter 91 may be embodied in' many forms. For example, it might be a conventional three stage ybinary counter reset to a count of 010 upon termination of thel T5 timing pulse on terminal 48. The T5 timing pulse is also applied to the reset input of read flip-flop 83. This disables gate 84 and sequencing oscillator 85 no longer delivers sequencing pulses, thereby terminating the read operation. The T5 timing pulses are also applied to the input of buffer 88 to reset the offset flip-flop 20 land through buffer 73 and delay unit 75, to the set input of sweep control llipfop 74, thereby enabling gate 76 to pass count pulses from counter oscillator 77 to terminal 17 whereby the count in counter 16 is again stepped until the next compare signal is provided.

Upon completion of a digitalizing cycle, a carry pulse applied to terminal 31 is passed by bulfe-r 78 to initiate the sequence of events just described in connection with transferring the count in the counter 16 into storage. However, since the carry pulse also sets frame read flipllop 32 (FIG. 1), Vthe count transferred is from frame counter 33 instead. rIihe cai-ry pulse is `also applied to buffer 84a to provide a pulse for resetting the sweep control flip-iiop 74.

The carry pulse also resets hold flip-dop 71, causing the hold potential to be removed from terminal 35. This allows each hold circuit 10 to sample the analog signal output from the associated amplifier 13'.

Referring to FIG. 3, there is shown a schematic circuit diagram of a portion of storage register 28 arranged to accept and store the digital number associated with a channel or the frame together with the input buffers. The storage register -consists essentially of fou-r conventional magnetic core shift registers. Each core 101 has an input winding 102 and an output winding 103. Positive pulses from the output Winding 103 of one core rare coupled to the input winding 102 of the following core by a diode 104 and a delay network formed of capacitor and a resistor 1106. The cores in column 1 also include a data input winding 107 which accepts the data words transmitted over cable 4S. A shift line 111 is connected between terminal 112` and a source of positive potential applied to terminal 113. This line is threaded through each core in the portion so that when it carries current in response to a shift pulse, all the cores in that portion are then reset to the Zero state. Upon termin-ation of such a shift pulse, data is transferred to the right. Terminal 112 is connected to the output of a respective amplifier 47 shown in FIG. 1. Since the core stages are alike, reference numerals are applied only to the core land associated circuitry in row l, colulmn 1.

All the data input windings 107 in a particular row are connected in series between an input buffer and a source of positive potential on Iterminal 1114.

The data input windings of row l receive signals from a tive-line buffer 115. From the labeled input terminals,

. 7M it is seen that this buffer of the least signicant digit and the most heavily weighted binary bit of the different decimal digits.

The data input windings of rows Zand 3 lare energized Vtative of the different decimal digits.

It will be recalled from the discussion of FIG. 1, that only one YIword is inserted into storage at a time. Thus, at any one instant of time not more than one input line of each buffer is activated. When a buffer inputline is made negative, signifying the presence of a weighted bit in Y the word then being stored, current ows through all the input windings 107 of that row to set each column 1 core in that row into the One state. It will be recalled that Ian amplified shifty pulse yfrom the 'associated ampliiier 53 precedes the insertion of data into a portion of the storage register 28 so that the columnrl in each portion selected tfor accepting data then stores the rst input Word. '[lhe shift pulse preceding the timing pulse Til vshifts the data in column lfinto column 2 `and clears column l 4to accept the second word for storage. This sequence is'repeated until after the shift pulse which precedes the timing pul-se T5, the digital number is stored in colu-mns 2-5.

yln the channel portions of storage register 28, the least significant digit-and sign resides in rows y1 and 4, respectively, of column 5; and the units, tens and hundredths decimal digits, in `columns 4, 3 and 2,V respectively. In the frame count portion, the unit tens, hundredths and thousandths decimal digits are then stored in columns 5, 4, 3 and 2, respectively. At the conclusion of a digitalizing cycle in which all the channels are converted shiftpulses may be applied to terminal 55, causing the data then in all .the cores tolbe shifted out in sequence o-n output terminals 12. The data signals on output terminal 12 may be transferred to the internal storage of Va digit-al computer or transferred to magnetic tape or .Y cards by suitable well-known techniques.

Referring to FIG. 4, there is shown a schematic circuit diagram of a preferred embodiment of the multitar comparator 14'. When the decoded analog signal on terminal 22 assumes a potential just below that of the held input analog signal on terminal 121, a signal is .provided on terminal 122 for setting the lassociated channel comparison flip-flop 15.

Thiscircuit is seen to comprise tubes V1 andVZ and associated circuitry. An inductor 123 and' capacitor 124 yare connected in series between the cathode of tube V1 and negative terminal 120. A resistor 125 provides :a D.C. eturn to ground for the grid of tube V1. A second inductor 126, inductively coupled to inductor 123, a

diode D1 `and -a coupling capacitor 127 are connected in series between terminal 22 and the grid of tube V1. A diode D2 shunted by resistor 131 is connected between e terminal 121 and the junction of diode D1 and capacitor 127. A plate Iload resistor 132A is connected between the plate of tube V1 `and positive terminal 133. Y

The plate of tube V'1 is coupled to the grid of-tube V2 by the resistance-capacitance coupling network 134. TheV plate of tube V2 is connected to positive terminal 1,33;

The cathode of tube V2 is connected to the junction of inductor 123 and capacitor 124. A cathode resistor i135 is connected between the cathode of tube V2 and negative terminal 120.

accepts signals representativeV lso beginning of a conversionv cycle, the potential on terminal V22 normally exceeds that of the held input analog signal applied on terminal 121 and diodes D1 and D2 are nonccnductive. The decoded analog potential is stepped downward during theycourse Yof a conversion cycle until substantially equal to that on 4terminal 121. Diodes D1 and D2 then conduct causing current to flow through inductor 126 and reducing the potential on .the grid of tube V1. This reduces the plate current 'li-owing through inductor y123.Y Inductors 123 and -126 |are relatively oriented as indicated by the dots so that the reduction of 'plate current induces a potential across inductor 126 tending to drive the grid of tube V1 still more negative. This regenerative action rapidly cuts tube V1 off, causing its plate potential to rise.

,The rise in plate potential of tube V1 is coupled by network 134 to the grid of tube V2 to render this tube conductive. With tube V2 conducting, the potential between grid and cathode of tube V1 is `sufficient to main` tain the latter tube 'cut cfr for the remainder of the conversion cycle. At the end of the conversion cycle, a carry pulse applied to the grid of tube V2 renders this tube nonconductive, allowing tube V1 yto return into conduction. The rise in potential on the plate of tube V1 upon being cut oli is diferentiated and utilized to set the associated comparison ip-op 15.

4l1`ube V2 and associated circuitry performs an important function in preventing tube V1 -from functioning as a blocking oscillator. Such operation would result in additional undesired settings of comparison llip-flop 15 during theremainder of the conversion cycle. With the circuit shown in FIG. Y4, only one setting pulse is `delivered for eacheonversion cycle. This circuit cooperates with comparison flip-flop 15to enable a compare potential to be delivered by the latter only'once per conversion cycle. If a comparison flip-flop 15 were not'included, only a short pulse derived by differentiating the potential waveform on terminal 122 would be available for enabling the different gates. The waveform itself could notbe used because it would indicate a comparison for the remainder of the conversion cycle. Thus, each comparison flip-flop Vin cooperation with the circuit of FIG. 4 provides a single unambiguous comparison indication during each conversion cycle of the desired duration and amplitude to condition the logical circuitry to eiTect the appropriate transfer of data signals into storage.

There has 'been described a system for substantially simultaneously sampling and converting a number of input analog signals into digital form 'with greataccuracy and at relatively high speed while minimizing the number of precision components required. yWhile a number of specific components have been described in detail, this is only for illustrative purposes. It is apparent that those `skilled in the art may now make numerous modifications of and departures from the specific apparatus described herein without departing from the 'inventive concepts. Consequently, the invention is to be construed as limited only by the spirit and scope'of the'appended claims.

1. Analog to digital conversion apparatus comprising, a plurality of input channels each adapted to receive a Y separate input analog signal, means for providing an electrical indication of a digital numberwhose value normally changes periodically by increments corresponding to the smallest change in its least significant digit, means responsive to said electrical indications for providing a decoded analog signal characteristic of the value of said digital number, means for simultaneously comparing said `decoded analog signal with said input analog signals to provide a compare signal identifying those Vchannels having an input analog signal then differing from said decoded Yanalog signal by less than a predetermined magnitude, said predetermined magnitude being less than or equal to the change in said decoded analog signal corresponding toa single one of said increments, storage means having portions therein corresponding respectively to each of said input channels, means responsive to said compare signal for temporarily preventing changes in the value of said digital number, means responsive to said compare signal and said electrical indication for storing the value of said digital number then indicated in said portions associated with respective input channels then identiiied by said compare signal, means for causing the value of said digital number to resume said normal periodic changes after storing said number, means responsive to said digital number reaching the end of a sequence of said changes whereby all said input analog signals have been converted into `digital form and stored in said storage means for converting said stored digital numbers into electrical output signals in digital form, said electrical out-put signals in digital form being provided in sequence on parallel output lines, a frame counter for storing a frame number in digital form to identify each of said sequence of changes, and means responsive to said digital number reaching said end of said squence for transferring said frame number in digital form to said storage means.

2. Analog to digital conversion apparatus comprising, a plurality of input channels each adapted to receive a separate input analog signal, a counter providing an electrical indication of the count therein, means responsive to said electrical indication for providing a decoded analog signal characteristic of the value of said count, a source of counting pulses, means for coupling said counting pulses to said counter, each applied pulse advancing by one said count therein, means for simultaneously coupling said decoded analog signal to said plurality of channels, a comparator in each channel for comparing a respective input signal with said decoded analog signal and providing a compare signal when the difference therebetween is less than a predetermined magnitude, said predetermined magnitude being less than or equal to the change in said decoded analog signal caused by said count advancing by one, means responsive to said compare signal for temporarily decoupling said counting pulses from said counter whereby said count remains temporarily unchanged, storage means having portions therein corresponding respectively to each of said input channels, means responsive to said compare signal and said electrical indication for storing in digital form said temporarily unchanged count in those portions of said storage means associated with input channels having comparators then providing a compare signal, means for again coupling said counting pulses to said counter after storing said temporarily unchanged count, said counter providing a carry pulse after changing from a predetermined count, and means responsive said carry pulse for converting said stored terporarily unchanged counts into characteristic electrical output signals in digital form.

3.k Apparatus in accordance with claim 2 wherein said electrical output signals in digital form are provided in sequence on parallel output lines.

4. Apparatus in accordance with claim 2 and further comprising, a frame counter for storing a frame number in digital form identifying a cycle occurring between sucl@ cessive carry pulses in which each of said input analog signals is converted into a stored digital number, and means responsive to said carry pulse for storing the frame number then in said frame counter in an associated portion of said storage means and then Kadvancing said frame counter by one.

5. Apparatus in accordance with claim 2 wherein said comparator comprises a comparison dip-flop, firs-t and second signal amplifying devices respectively conductive and nonconductive initially, means responsive to amplitude coincidence of said input analog and said decoded analog signals for reversing the conductive states of said first and second devices, means responsive to said reversal of conductive states for setting said comparison flip-flop to provide said compare signal, coduction of said second device maintaining said first device nonconductive, and means responsive to said carry pulse for returning said first and second devices to said initial conducting states.

,16. Analog to ldigital conversion apparatus comprising, a plurality of input channels each adapted to receive a separate input analog signal, a counter providing an electrical indication of the count therein, means responsive to said electrical indication for providing a decoded analog signal characteristic of the value of said count, a source of counting pulses, means for coupling said counting pulses to said counter, each applied pulse advancing by one said count therein, means for simultaneously coupling said decoded analog signal to said plurality of channels, a comparator in each channel for comparing a respective input signal with said decoded analog signal and providing a compare signal when the difference therebetween is less than a predetermined magnitude, said predetermined magnitude being less than or equal to the change in said decoded analog signal caused by said count advancing by one, means responsive to said compare signal for temporarily decoupling said counting pulses from said counter whereby said count remains temporarily unchanged, storage means having portions therein corresponding respectively to each of said input channels, means responsive to said compare signal and said electrical indication for storing in digital form said temporarily unchanged count in those portions of said storage means associated with input channels having comparators then providing a compare signal, and means for offsetting said decoded analog signal during time intervals when said count is temporarily unchanged to prevent a false compare signal from then being generated.

7. Apparatus in accordance with claim 6 and further comprising means for holding all said input analog signals to respective levels determined at the same instant of time, said levels being converted into digital form and stored.

References Cited in the tile of this patent UNITED STATES PATENTS 2,568,724 Earp et al Sept. 25, 1951 2,753,546 Knowles July 3, 1956 2,828,482 Schumann Mar. 25, 1958 

1. ANALOG TO DIGITAL CONVERSION APPARATUS COMPRISING, A PLURALITY OF INPUT CHANNELS EACH ADAPTED TO RECEIVE A SEPARATE INPUT ANALOG SIGNAL, MEANS FOR PROVIDING AN ELECTRICAL INDICATION OF A DIGITAL NUMBER WHOSE VALUE NORMALLY CHANGES PERIODICALLY BY INCREMENTS CORRESPONDING TO THE SMALLEST CHANGE IN ITS LEAST SIGNIFICANT DIGIT, MEANS RESPONSIVE TO SAID ELECTRICAL INDICATIONS FOR PROVIDING A DECODED ANALOG SIGNAL CHARACTERISTIC OF THE VALUE OF SAID DIGITAL NUMBER, MEANS FOR SIMULTANEOUSLY COMPARING SAID DECODED ANALOG SIGNAL WITH SAID INPUT ANALOG SIGNALS TO PROVIDE A COMPARE SIGNAL IDENTIFYING THOSE CHANNELS HAVING AN INPUT ANALOG SIGNAL THEN DIFFERING FROM SAID DECODED ANALOG SIGNAL BY LESS THAN A PREDETERMINED MAGNITUDE, SAID PREDETERMINED MAGNITUDE BEING LESS THAN OR EQUAL TO THE CHANGE IN SAID DECODED ANALOG SIGNAL CORRESPONDING TO A SINGLE ONE OF SAID INCREMENTS, STORAGE MEANS HAVING PORTIONS THEREIN CORRESPONDING RESPECTIVELY TO EACH OF SAID INPUT CHANNELS, MEANS RESPONSIVE TO SAID COMPARE SIGNAL FOR TEMPORARILY PREVENTING CHANGES IN THE VALUE OF SAID DIGITAL NUMBER, MEANS RESPONSIVE TO SAID COMPARE SIGNAL AND SAID ELECTRICAL INDICATION FOR STORING THE VALUE OF SAID DIGITAL NUMBER THEN INDICATED IN SAID PORTIONS ASSOCIATED WITH RESPECTIVE INPUT CHANNELS THEN IDENTIFIED BY SAID COMPARE SIGNAL, MEANS FOR CAUSING THE VALUE OF 